1. Field of the Invention
The present invention relates generally to electronic packaging technology and, more particularly, to a fabrication method of wafer level chip scale packages available for a three-dimensional package stack.
2. Description of the Related Art
As in other sectors of the semiconductor industry, the electronic packaging industry may be driven by a demand for packages that may be smaller, faster, cheaper, more reliable, and more multi-functional, for example. A chip scale package (CSP), which may be referred to as a chip size package, has been developed to satisfy the industry's growing demand for a small, i.e., chip-sized, form factor that may be suitably implemented in small and advanced electronic end-applications. Additionally, a wafer level chip scale package (WLCSP) has been introduced to realize cost-effective fabrication of CSPs on the wafer prior to singulation.
A three-dimensional package stack may employ the WLCSP as unit packages of the stack. The three-dimensional package stack may have electrical connections between upper and lower individual unit packages. Two conventional approaches for offering electrical connections to the WLCSP stack are discussed separately below.
According to one conventional approach, a semiconductor wafer may be thinned using a grinding technique, and then a hole may be formed that extends completely through the semiconductor wafer. A wiring plug may be formed in the hole, and a metal bump may be formed on the wiring plug. The metal bump may be connected to the wiring plug of an underlying semiconductor wafer, so that adjacent upper and lower packages may be electrically coupled to each other.
Although the conventional approach described above may generally provide acceptable results, it is not without shortcomings. For example, the wafer, which may be fabricated from silicon, may be inherently brittle. Thus, a relatively thin wafer (which may result after grinding) may not exhibit good reliability during fabrication and handling. Further, it may be difficult to form the wiring plug in the hole penetrating completely through the wafer. Moreover, the formation of the metal bump may require a complicated, lengthy and expensive process since the metal bump may be typically formed by photolithography and electroplating techniques.
According to another conventional approach, a hole may be partially formed in a relatively thick wafer, and a wiring plug may be formed in the hole. Then the wafer may be thinned using a grinding technique, and the ground face of the wafer may be selectively etched until the wiring plug is exposed. A protrusion may formed on an exposed portion of the wiring plug, and a solder ball may be formed to surround the protrusion.
This conventional approach may generally provide acceptable results, however, it is not without shortcomings. For example, the etching process as one of thinning techniques may be relatively complicated, lengthy and susceptible to delicate process conditions as compared to the mechanical grinding process. The etching process may also damage the wiring plug. Additionally, a process of forming the solder ball may be complicated and lengthy due to the presence of the protrusion, and because the solder balls may be individually positioned on the protrusions.